Use cases & realizations

Use cases & fit

Platforms: superconducting-2d-grid neutral-atom-reconfigurable

Tasks: memory computation

Physical realizations

• Google superconducting square-grid processors demonstrated

  Scaling from distance 3 to distance 5 reduced logical error per cycle from the distance-3 ensemble average 3.028% ± 0.023% to 2.914% ± 0.016%. This is the 2023 distance-scaling result; it did not report the later Willow suppression factor.

  References: google2023suppressing

• Google Willow superconducting processor demonstrated

  A distance-7 patch reached 0.143% ± 0.003% logical error per cycle and each distance increase of two suppressed error by Λ = 2.14 ± 0.02, with logical lifetime beyond the best physical qubit.

  References: google2024below

• Google Willow dynamic superconducting layouts demonstrated

  Hexagonal-connectivity, walking data/measure-role, and iSWAP-based surface-code schedules all showed distance-dependent error suppression, demonstrating that the code can be adapted to connectivity, leakage, and native-gate constraints.

  References: eickbusch2024dynamic

• USTC Zuchongzhi 2.1 superconducting processor demonstrated

  A 17-qubit distance-3 Surface-17 patch executed repeated correction cycles, providing an independent superconducting realization of a planar surface-code memory.

  References: zhao2022realization

• reconfigurable neutral-atom arrays demonstrated

  Movable atoms realized surface-code patches inside a multi-code logical processor and enabled transversal inter-patch entangling gates by aligning corresponding data qubits. This is a logical-operations demonstration, not a below-threshold surface-memory claim; for the distance-five and distance-seven surface blocks, logical input-state preparation was not itself fault-tolerant.

  References: bluvstein2024logical