Entry facet
Use cases & realizations
Where the code fits and what has been demonstrated.
Use cases & fit
Platforms: majorana-parity-measurement superconducting-dynamic-circuit spin-photonic
Tasks: memory measurement-driven-logical-operations
Physical realizations
IBM Falcon superconducting processor demonstrated
A preliminary hardware study measured plaquette stabilizers of the original Floquet schedule and reported syndrome-change rates. It did not demonstrate a protected logical memory, distance scaling, or logical error suppression.
References: wootton2022plaquettes
Majorana-tetron parity-measurement architecture proposed
Native pair-parity measurements and planar layouts were simulated with Majorana-specific faults. This is an architecture and decoder study, not a laboratory realization of a logical honeycomb memory.
References: karzig2017majorana, paetznick2023majorana
spin-optical photonic architecture proposed
A co-designed photonic implementation was benchmarked numerically under its loss and hardware assumptions. Its simulated loss threshold is not an experimental honeycomb threshold.
References: dessertaine2026photonic
ancilla-free dynamic superconducting circuit proposed
Data and measurement roles change during the cycle to remove dedicated ancillas, clear leakage, and improve timelike distance. The result is a simulated circuit proposal with a different detector model.
References: claes2025dynamic